To speed up time-to-market for automotive partners, ARM has been adding more functional safety capabilities to M-profile cores and certifying them with an external assessor for ISO 26262. The updated Cortex-M23 means the full portfolio of Cortex-M microcontrollers, including Cortex-M85 and Cortex-M55, now include functional safety features.
Despite being launched in 2016, the Cortex-M23 remains ARM’s most power-efficient Cortex-M CPU and has been updated to include additional diagnostic coverage for safety-critical applications. Examples include ultrasonic parking sensors for parking assistance, tire pressure and rain sensors, lighting and LED controllers for headlights and brake lights. Many of these applications require ASIL B, a medium level of integrity. Programmable Logic Ics
ASIL B level normally requires the detection of 90 percent of single point faults, and that transient faults are addressed, if applicable. Transient faults are tricky in that they can go easily undetected. This is because a particle could hit an area of the design and flip one bit of data, but it is not long before the next bit of data is written to that location, overwriting the flipped bit says Laura Armitstead, Product Manager for ARM’s Automotive line of business.
The updated Cortex-M23 adds transient fault protection to address this issue for applications that are constrained by area and cost where a dual-core lockstep approach would be undesirable. It also adds interface protection for the detection of faults at the boundary of the CPU, removing more work at the system level for chip designers.
The use of a Software Test Library for Cortex-M23 would also provide more diagnostic coverage of permanent faults, complementing the internal core safety mechanisms. These additional features have no impact on benchmark performance compared to the previous Cortex-M23, making adoption simpler.
For applications where dual-core lockstep is required, there is a new Dual Core Lockstep application note specific to Cortex-M23. This document gives guidance on how to implement this feature on Cortex-M23 and what to watch out for when implementing it. This might also be appropriate for an ASIL B application if there is additional die area and power available for a dual core design.
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